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low distortion, high speed rail-to-rail input/output amplifiers ad8027/ad8028 features high speed 190 mhz, C3 db bandwidth (g = +1) 100 v/s slew rate low distortion 120 dbc @ 1 mhz sfdr 80 dbc @ 5 mhz sfdr selectable input crossover threshold low noise 4.3 nv/ hz 1.6 pa/ hz low offset voltage: 900 v max low power: 6.5 ma/amplifier supply current power-down mode no phase reversal: v in > |v s | + 200 mv wide supply range: 2.7 v to 12 v small packaging: soic-8, sot-23-6, msop-10 applications filters adc drivers level shifting buffering professional video low voltage instrumentation general description the ad8027/ad8028 1 is a high speed amplifier with rail-to- rail input and output that operates on low supply voltages and is optimized for high performance and wide dynamic signal range. the ad8027/ad8028 has low noise (4.3 nv/ hz , 1.6 pa/ hz ) and low distortion (120 dbc @ 1 mhz). in appli- cations that use a fraction of or the entire input dynamic range and require low distortion, the ad8027/ad8028 is an ideal choice. many rail-to-rail input amplifiers have an input stage that switches from one differential pair to another as the input sig- nal crosses a threshold voltage, which causes distortion. the ad8027/ad8028 has a unique feature that allows the user to select the input crossover threshold voltage through the select pin. this feature controls the voltage at which the complementary transistor input pairs switch. the ad8027/ ad8028 also has intrinsically low crossover distortion. connection diagrams sot-23-6 (rt) v out 1 ?v s 2 +in 3 5 6 +v s disable/select 4 ?in +? 03327-b-001 nc = no connect nc soic-8 (r) 1 ?in 2 +in 3 ?v s 4 +v s v out nc 8 7 6 5 disable/select v outb ?in b +in b 8 7 6 5 +v s v outa soic-8 (r) 1 ?in a 2 +in a 3 ?v s 4 + ? + ? v outb 10 9 +v s disable/select b ?in b +in b 8 7 6 disable/select a v outa msop-10 (rm) 1 ?in a 2 +in a 3 ?v s 4 5 + ? + ? figure 1. connection diagrams (top view) with its wide supply voltage range (2.7 v to 12 v) and wide bandwidth (190 mhz), the ad8027/ad8028 amplifier is designed to work in a variety of applications where speed and performance are needed on low supply voltages. the high per- formance of the ad8027/ad8028 is achieved with a quiescent current of only 6.5 ma/amplifier typical. the ad8027/ad8028 has a shut down mode that is co ntrolled via the select pin. the ad8027/ad8028 is available in soic-8, msop-10, and sot-23-6 packages. they are rated to work over the industrial temperature range of C40c to +125c. output voltage (v p-p) 012345678910 ?140 ?120 ?100 ?80 ?60 ?40 ?20 sfdr (db) g = +1 frequency = 100khz r l = 1k ? v s = 5v v s = +3v v s = +5v 03327-a-063 figure 2. sfdr vs. output amplitude 1 protected by u.s. patent numbers 6,486,737b1; 6,518,842b1 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2003 analog devices, inc. all rights reserved.
ad8027/ad8028 rev. b | page 2 of 24 table of contents specifications..................................................................................... 3 absolute maximum ratings............................................................ 6 maximum power dissipation ..................................................... 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 16 input stage................................................................................... 16 crossover selection .................................................................... 16 output stage................................................................................ 17 dc errors .................................................................................... 17 wideband operation ..................................................................... 18 circuit considerations .............................................................. 19 applications..................................................................................... 20 using the ad8027/ad8028 select pin ............................... 20 driving a 16-bit adc ................................................................ 20 band-pass filter.......................................................................... 21 design tools and technical support ....................................... 21 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 23 revision history revision b: 10/03data sheet changed from rev. a to rev. b changes to figure 1...........................................................................1 revision a: 8/03data sheet changed from rev. 0 to rev. a addition of ad8028........................................................... universal changes to general description.........................................1 changes to figures 1, 3, 4, 8, 13, 15, 17............................ 1, 6, 7, 8, 9 changes to figures 58, 60 .........................................................18, 20 changes to specifications........................................................3 updated outline dimensions .............................................22 updated ordering guide.......................................................23 revision 0: initial version
ad8027/ad8028 rev. b | page 3 of 24 specifications table 1. v s = 5 v (@ t a = 25c, r l = 1 k? to midsupply, g = +1, unless otherwise noted.) parameter conditions min typ max unit dynamic performance g = +1, v o = 0.2 v p-p 138 190 mhz C3 db bandwidth g = +1, v o = 2 v p-p 20 32 mhz bandwidth for 0.1 db flatness g = +2, v o = 0.2 v p-p 16 mhz slew rate g = +1, v o = 2 v step/g = C1, v o = 2 v step 90/100 v/s settling time to 0.1% g = +2, v o = 2 v step 35 ns noise/distortion performance f c = 1 mhz, v o = 2 v p-p, r f = 24.9 ? 120 dbc spurious free dynamic range (sfdr) f c = 5 mhz, v o = 2 v p-p, r f = 24.9 ? 80 dbc input voltage noise f = 100 khz 4.3 nv/ hz input current noise f = 100 khz 1.6 pa/ hz differential gain error ntsc, g = +2, r l = 150 ? 0.1 % differential phase error ntsc, g = +2, r l = 150 ? 0.2 degree crosstalk, output to output g = +1, r l =100 ?, v out = 2 v p-p, v s = 5 v @ 1 mhz C93 db dc performance input offset voltage select = tri-state or open, pnp active 200 800 v select = high npn active 240 900 v input offset voltage drift t min to t max 1.50 v/c v cm = 0 v, npn active 4 6 a input bias current 1 t min to t max 4 a v cm = 0 v, pnp active C8 C11 a input bias current 1 t min to t max C8 a input offset current 0.1 0.9 a open-loop gain v o = 2.5 v 100 110 db input characteristics input impedance 6 m? input capacitance 2 pf input common-mode voltage range C5.2 to +5.2 v common-mode rejection ratio v cm = 2.5 v 90 110 db select pin crossover lowselection input voltage C3.3 to +5 v crossover highselection input voltage C3.9 to C3.3 v disable input voltage tri-state < 20 a C5 to C3.9 v disable switching speed 980 ns enable switching speed 50% of input to <10% of final v o 45 ns output characteristics output overdrive recovery time (rising/falling edge) v i = +6 v to C6 v, g = C1 40/45 ns output voltage swing Cv s + 0.10 +v s C 0.06, Cv s + 0.06 +v s C 0.10 v short circuit output sinking and sourcing 120 ma off isolation v in = 0.2 v p-p, f = 1 mhz, select = low C49 db capacitive load drive 30% overshoot 20 pf power supply operating range 2.7 12 v quiescent current/amplifier 6.5 8.5 ma quiescent current (disabled) select = low 370 500 a power supply rejection ratio v s 1 v 90 110 db 1 no sign or a plus indicates current into pin, minus indicates current out of pin.
ad8027/ad8028 rev. b | page 4 of 24 specifications table 2. v s = +5 v (@ t a = 25c, r l = 1 k to midsupply, unless otherwise noted.) parameter conditions min typ max unit dynamic performance g = +1, v o = 0.2 v p-p 131 185 mhz ?3 db bandwidth g = +1, v o = 2 v p-p 18 28 mhz bandwidth for 0.1 db flatness g = +2, v o = 0.2 v p-p 12 mhz slew rate g = +1, v o = 2 v step/g = ?1, v o = 2 v step 85/100 v/s settling time to 0.1% g = +2, v o = 2 v step 40 ns noise/distortion performance f c = 1 mhz, v o = 2 v p-p, r f = 24.9 90 dbc spurious free dynamic range (sfdr) f c = 5 mhz, v o = 2 v p-p, r f = 24.9 64 dbc input voltage noise f = 100 khz 4.3 nv/ hz input current noise f = 100 khz 1.6 pa/ hz differential gain error ntsc, g = +2, r l = 150 0.1 % differential phase error ntsc, g = +2, r l = 150 0.2 degree crosstalk, output to output g = 1, r l = 100 , v out = 2 v p-p, v s = 5 v @ 1 mhz ?92 db dc performance input offset voltage select = tri-state or open, pnp active 200 800 v select = high npn active 240 900 v input offset voltage drift t min to t max 2 v/c v cm = 2.5 v, npn active 4 6 a input bias current 1 t min to t max 4 a v cm = 2.5 v, pnp active ?8 ?11 a input bias current 1 t min to t max ?8 a input offset current 0.1 0.9 a open-loop gain v o = 1 v to 4 v 96 105 db input characteristics input impedance 6 m input capacitance 2 pf input common-mode voltage range ?0.2 to +5.2 v common-mode rejection ratio v cm = 0 v to 2.5 v 90 105 db select pin crossover low?selection input voltage 1.7 to 5 v crossover high?selection input voltage 1.1 to 1.7 v disable input voltage 0 to 1.1 v disable switching speed 1100 ns enable switching speed tri-state < 20 a 50% of input to <10% of final v o 50 ns output characteristics overdrive recovery time (rising/falling edge) v i = ?1 v to +6 v, g = ?1 50/50 ns output voltage swing r l = 1 k ?v s + 0.08 +v s ? 0.04, ?v s + 0.04 +v s ? 0.08 v off isolation v in = 0.2 v p-p, f = 1 mhz, select = low ?49 db short circuit current sinking and sourcing 105 ma capacitive load drive 30% overshoot 20 pf power supply operating range 2.7 12 v quiescent current/amplifier 6 8.5 ma quiescent current (disabled) select = low 320 450 a power supply rejection ratio v s 1 v 90 105 db 1 no sign or a plus indicates current into pin, minus indicates current out of pin.
ad8027/ad8028 rev. b | page 5 of 24 specifications table 3. v s = +3 v (@ t a = 25c, r l = 1 k to midsupply, unless otherwise noted.) parameter conditions min typ max unit dynamic performance g = +1, v o = 0.2 v p-p 125 180 mhz ?3 db bandwidth g = +1, v o = 2 v p-p 19 29 mhz bandwidth for 0.1 db flatness g = +2, v o = 0.2 v p-p 10 mhz slew rate g = +1, v o = 2 v step/g = ?1, v o = 2 v step 73/100 v/s settling time to 0.1% g = +2, v o = 2 v step 48 ns noise/distortion performance f c = 1 mhz, v o = 2 v p-p, r f = 24.9 : 85 dbc spurious free dynamic range (sfdr) f c = 5 mhz, v o = 2 v p-p, r f = 24.9 : 64 dbc input voltage noise f = 100 khz 4.3 nv/ hz input current noise f = 100 khz 1.6 pa/ hz differential gain error ntsc, g = +2, r l = 150 0.15 % differential phase error ntsc, g = +2, r l = 150 0.20 degree crosstalk, output to output g = 1, r l = 100 , v out = 2 v p-p, v s = 3 v @ 1 mhz ?89 db dc performance select = tri-state or open, pnp active 200 800 v input offset voltage select = high npn active 240 900 v input offset voltage drift t min to t max 2 v/c v cm = 1.5 v, npn active 4 6 a input bias current 1 t min to t max 4 a v cm = 1.5 v, pnp active ?8 ?11 a input bias current 1 t min to t max ?8 a input offset current 0.1 0.9 a open-loop gain v o = 1 v to 2 v 90 100 db input characteristics input impedance 6 m input capacitance 2 pf input common-mode voltage range r l = 1 k ?0.2 to +3.2 v common-mode rejection ratio v cm = 0 v to 1.5 v 88 100 db select pin crossover low?selection input voltage 1.7 to 3 v crossover high?selection input voltage 1.1 to 1.7 v disable input voltage 0 to 1.1 v disable switching speed 1150 ns enable switching speed tri-state < 20 a 50% of input to <10% of final v o 50 ns output characteristics output overdrive recovery time (rising/falling edge) v i = ?1 v to +4 v, g = ?1 55/55 ns output voltage swing r l = 1 k ?v s + 0.07 +v s ? 0.03, ?v s + 0.03 +v s ? 0.07 v short circuit current sinking and sourcing 72 ma off isolation v in = 0.2 v p-p, f = 1 mhz, select = low ?49 db capacitive load drive 30% overshoot 20 pf power supply operating range 2.7 12 v quiescent current/amplifier 6.0 8.0 ma quiescent current (disabled) select = low 300 420 a power supply rejection ratio v s 1 v 88 100 db 1 no sign or a plus indicates current into pin, minus indicates current out of pin.
ad8027/ad8028 rev. b | page 6 of 24 absolute maximum ratings table 4. parameter rating supply voltage 12.6 v power dissipation see figure 3 common-mode input voltage v s 0.5 v differential input voltage 1.8 v storage temperature C65c to +125c operating temperature range C40c to +125c lead temperature range (soldering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rat- ing only; functional operation of the device at these or any other conditions above those indicated in the operational sec- tion of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum power dissipation the maximum safe power dissipation in the ad8027/ad8028 package is limited by the associated rise in junction temperature (t j ) on the die. the plastic encapsulating the die will locally reach the junction temperature. at approximately 150c, which is the glass transition temperature, the plastic will change its properties. even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ad8027/ad8028. exceeding a junction temperature of 175c for an extended period of time can result in changes in the silicon devices, potentially causing failure. the still-air thermal properties of the package and pcb ( ja ), ambient temperature (t a ), and the total power dissipated in the package (p d ) determine the junction temperature of the die. the junction temperature can be calculated as ( ) ja d a j p t t + = the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). assuming the load (r l ) is referenced to midsupply, then the total drive power is v s /2 i out , some of which is dissipated in the package and some in the load (v out i out ). the difference between the total drive power and the load power is the drive power dissipated in the package. ( ) + = () l out l out s s s d r v r v v i v p 2 C 2 ? ? ? ? ? ? ? ? + = rms output voltages should be considered. if r l is referenced to v sC , as in single-supply operation, then the total drive power is v s i out . if the rms signal levels are indeterminate, then consider the worst case, when v out = v s /4 for r l to midsupply () () l s s s d r v i v p 2 4 / + = in single-supply operation with r l referenced to v s C, worst case is v out = v s /2. airflow will increase heat dissipation, effectively reducing ja . also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes will reduce the ja . care must be taken to minimize parasitic capaci- tances at the input leads of high speed op amps as discussed in the board layout section. figure 3 shows the maximum safe power dissipation in the package versus the ambient temperature for the soic-8 (125c/w), sot-23-6 (170c/ w), and msop-10 (130c/w) packages on a jedec standard 4-layer board. output short circuit shorting the output to ground or drawing excessive current from the ad8027/ad8028 will likely cause catastrophic failure. ambient temperature (c) maximum power dissipation (w) ?55 ?35 ?15 5 25 45 65 85 105 125 0 0.5 1.0 1.5 2.0 sot-23-6 soic-8 msop-10 03327-a-002 figure 3. maximum power dissipation
ad8027/ad8028 rev. b | page 7 of 24 typical performance characteristics default conditions v s = +5 v (t a = +25c, r l = 1 k?, unless otherwise noted.) frequency (mhz) 0.1 1 10 100 1000 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 normalized closed-loop gain (db) v out = 200mv p-p 03327-a-003 ad8027 g = +1 ad8028 g = +1 g = +10 g = ?1 g = +2 figure 4. small signal frequency response for various gains frequency (mhz) 0.1 1 10 100 1000 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 closed- loop gain (db) g = +1 v out = 200mv p-p v s = +5v v s = 5v v s = +3v v s = +3v r f = 24.9 ? 03327-a-004 figure 5. ad8027 small signal frequency response for various supplies 100 frequency (mhz) 0.1 1 10 1000 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 closed-loop gain (db) g = +1 v out = 2v p-p v s = +5v v s = 5v v s = +3v 03327-a-005 figure 6. large signal frequency response for various supplies frequency (mhz) 0.1 1 10 100 1000 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 closed-loop gain (db) g = +2 v out = 200mv p-p v s = +5v v s = 5v v s = +3v 03327-a-006 figure 7. small signal frequency response for various supplies frequency (mhz) 0.1 1 10 100 1000 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 closed-loop gain (db) g = +1 v out = 200mv p-p 03327-a-007 v s = 5v v s = +5v v s = +3v figure 8. ad8028 small signal frequency response for various supplies frequency (mhz) 0.1 1 10 100 1000 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 closed-loop gain (db) g = +2 v out = 2v p-p v s = 5v v s = +3v v s = +5v 03327-a-008 figure 9. large signal frequency response for various supplies
ad8027/ad8028 rev. b | page 8 of 24 frequency (mhz) 0.1 1 10 100 1000 closed-loop gain (db) g = +1 v out = 200mv p-p ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 c l = 0pf c l = 20pf c l = 5pf 03327-a-009 figure 10. ad8027 small signal frequency response for various c load frequency (mhz) 0.1 1 10 100 1000 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 closed-loop gain (db) g = +2 v out = 200mv p-p v out = 2v p-p v out = 4v p-p 03327-a-010 figure 11. frequency response for various output amplitudes frequency (mhz) 0.1 1 10 100 1000 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 1 0 2 closed-loop gain (db) +125c ?40c +25c 03327-a-011 g = +1 v out = 200mv p-p figure 12. ad8027 small signal frequency response vs. temperature frequency (mhz) 0.1 1 10 100 1000 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 3 2 closed-loop gain (db) 03327-a-012 c l = 0pf c l = 20pf c l = 5pf g = +1 v out = 200mv p-p figure 13. ad8028 small signal frequency response for various c load frequency (mhz) 0.1 1 10 100 1000 ?4 ?3 ?2 ?1 0 1 2 3 5 4 6 7 8 closed-loop gain (db) g = +2 v out = 0.2v p-p r l = 1k ? v out = 2.0v p-p r l = 1k ? v out = 2.0v p-p r l = 150 ? v out = 0.2v p-p r l = 150 ? 03327-a-013 figure 14. small signal frequency response for various r load values frequency (mhz) 0.1 1 10 100 1000 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 closed-loop gain (db) g = +1 v out = 200mv p-p 03327-a-014 +25c ?40c +125c figure 15. ad8028 small signal frequency response vs. temperature
ad8027/ad8028 rev. b | page 9 of 24 frequency (mhz) 0.1 1 10 100 1000 closed-loop gai (db) g = +1 v out = 200mv p-p ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 v icm = v s+ ? 0.2v select = high v icm = 0v select = high or tri v icm = v s? + 0.2v select = tri v icm = v s+ ? 0.3v select = high v icm = v s? + 0.3v select = tri 03327-a-015 figure 16. small signal frequency response vs. input common-mode voltages frequency (mhz) 0.001 0.01 0.1 1 10 100 1000 ?130 ?140 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 crosstalk (db) 03327-a-016 g = +1 v s = 5v r l = 1k ? a to b b to a crosstalk = 20log (v out /v in ) 1/2 ad8028 + u1 r3 1k ? r2 50 ? r1 50 ? v1 vi ? 1/2 ad8028 + u2 v out ? figure 17. ad8028 crosstalk output to output frequency (hz) open-loop gain (db) phase (degrees) 10 100 1k 10k 100k 1m 10m 100m 1g ?25 ?5 15 35 55 75 95 115 135 ?10 0 10 20 30 40 50 60 70 80 90 100 110 gain phase 03327-a-017 figure 18. open-loop gain and phase vs. frequency 1 10 100 1k 10k 100k frequency (hz) 1m 10m 100m 1g 10 100 current noise (pa/ hz) 1 10 100 voltage noise (nv/ hz) voltage current 03327-a-018 figure 19. voltage and current noise vs. frequency 100 frequency (mhz) 0.1 1 10 1000 5.9 6.0 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 closed-loop gain (db) g = +2 r l = 150 ? v out = 2v p-p v out = 200mv p-p 03327-a-019 figure 20. 0.1 db flatness frequency response
ad8027/ad8028 rev. b | page 10 of 24 frequency (mhz) 0.1 1 20 10 distortion (db) ?140 ?120 ?100 ?80 ?60 ?40 ?20 g = +1 v out = 2v p-p r l = 1k ? second harmonic: solid line third harmonic: dashed line v s = +3v v s = +5v v s = 5v 03327-a-020 figure 21. harmonic distortion vs. frequency and supply voltage output voltage (v p-p) 012345678910 ?140 ?120 ?100 ?80 ?60 ?40 ?20 distortion (db) g = +1 (r f = 24.9 ? ) frequency = 100khz r l = 1k ? v s = 5v v s = +3v v s = +5v second harmonic: solid line third harmonic: dashed line 03327-a-021 figure 22. harmonic distortion vs. output amplitude input common-mode voltage (v) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 distortion (db) ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 g = +1 (r f = 24.9 ? ) v out = 1.0v p-p @ 100khz r l = 1k ? second harmonic: solid line third harmonic: dashed line v s = +3v v s = +5v 03327-a-022 figure 23. harmonic distortion vs. input common-mode voltage, select = high frequency (mhz) 0.1 1 10 20 distortion (db) ?140 ?120 ?100 ?80 ?60 ?40 ?20 g = +1 (r f = 24.9 ? ) v out = 2.0v p-p second harmonic: solid line third harmonic: dashed line r l = 150 ? r l = 1k ? 03327-a-023 figure 24. harmonic distortion vs. frequency and load input common-mode voltage (v) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 distortion (db) ?125 ?115 ?105 ?95 ?85 ?75 ?65 ?55 ?45 g = +1 (r f = 24.9 ? ) v out = 1.0v p-p @ 2mhz select = high select = tri select = tri select = high second harmonic: solid line third harmonic: dashed line 03327-a-024 figure 25. harmonic distortion vs. input common-mode voltage, v s = +5 v input common-mode voltage (v) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 distortion (db) ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 g = +1 (r f = 24.9 ? ) v out = 1.0v p-p @ 100khz second harmonic: solid line third harmonic: dashed line v s = +3v v s = +5v 03327-a-025 figure 26. harmonic distortion vs. input common-mode voltage, select = tri -state or open
ad8027/ad8028 rev. b | page 11 of 24 frequency (mhz) 0.1 1 10 20 distortion (db) ?140 ?120 ?100 ?80 ?60 ?40 ?20 v s = +5 v out = 2.0v p-p second harmonic: solid line third harmonic: dashed line g = +2 g = +1 g = +10 03327-a-026 figure 27. harmonic distortion vs. frequency and gain ? 0.20 ? 0.15 ? 0.10 ? 0.05 0.05 0 0.10 0.15 0.20 g = +1 v s = 2.5v 20ns/div 50mv/div 03327-a-027 figure 28. small signal transient response ? 2.0 ? 1.0 0 1.0 2.0 100ns/div 500mv/div g = +1 v s = 2.5v v out = 4v p-p v out = 2v p-p 03327-a-028 figure 29. large signal transient response, g = +1 ? 2.5 ? 2.0 ? 1.5 ? 1.0 ? 0.5 0 0.5 1.0 1.5 2.0 2.5 g = +2 v s = 2.5v v out = 4v p-p v out = 2v p-p 20ns/div 50mv/div 03327-a-029 figure 30. large signal transient response, g = +2 ? 0.20 ? 0.15 ? 0.10 ? 0.05 0.05 0 0.10 0.15 0.20 g = +1 v s = 2.5v c l = 20pf c l = 5pf 20ns/div 50mv/div 03327-a-030 figure 31. small signal transient response with capacitive load ? 4.0 ? 3.0 ? 2.0 ? 1.0 0 1.0 2.0 3.0 4.0 ? 3.5 ? 2.5 ? 1.5 ? 0.5 0.5 1.5 2.5 3.5 50ns/div 500mv/div g = ?1 r l = 1k ? v s = 2.5v 03327-a-031 figure 32. output overdrive recovery
ad8027/ad8028 rev. b | page 12 of 24 ?4.0 ?3.0 ?2.0 ?1.0 0 1.0 2.0 3.0 4.0 ?3.5 ?2.5 ?1.5 ?0.5 0.5 1.5 2.5 3.5 50ns/div 500mv/div g = +1 r l = 1k ? v s = 2.5v 03327-a-032 figure 33. input overdrive recovery ?0.1% +0.1% 5 s/div v in (200mv/div) v out ? 2v in (2mv/div) g = +2 03327-a-033 figure 34. long-term settling time ?0.1% +0.1% 20ns/div v in (200mv/div) v out (400mv/div) v out ? 2v in (0.1%/div) 03327-a-034 figure 35. 0.1% short-term settling time temperature (c) input bias current (select = high) ( a) ?40 ?25 ?10 5 20 35 50 65 80 110 95 125 2.5 3.0 3.5 4.0 4.5 input bias current (select = tri) ( a) ?6.5 ?7.0 ?7.5 ?8.0 ?8.5 v s = +3v v s = +5v v s = 5v select = tri select = high 03327-a-035 figure 36. input bias current vs. temperature input common-mode voltage (v) input bias current ( a) 012345678910 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 v s = 5v select = tri v s = +3v v s = +5v select = high 03327-a-036 figure 37. input bias current vs. input common-mode voltage ?800 ?600 ?400 ?200 0 200 400 600 800 input offset voltage ( v) 0 50 100 150 200 250 frequency select = tri select = high count = 1780 select mean std. dev high 49 v 193 v tri 55 v 150 v 03327-a-037 figure 38. input offset voltage distribution
ad8027/ad8028 rev. b | page 13 of 24 temperature (c) input offset voltage ( v) ?40 ?25 ?10 5 20 35 50 65 80 110 95 125 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 select = tri v s = 5v v s = +5v select = high v s = +3v 03327-a-038 figure 39. input offset voltage vs. temperature input common-mode voltage (v) input offset voltage ( v) ?5?4?3?2?1012345 150 290 170 190 210 230 250 270 select = high select = tri v s = 5v 03327-a-039 figure 40. input offset voltage vs. input common-mode voltage, v s = 5 input common-mode voltage (v) input offset voltage ( v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 150 290 170 190 210 230 250 270 select = high select = tri v s = +5v 03327-a-040 figure 41. input offset voltage vs. input common-mode voltage, v s = +5 input common-mode voltage (v) input offset voltage ( v) 0 0.50 1.00 1.50 2.00 2.50 3.00 150 270 170 190 210 230 250 select = high select = tri v s = +3v 03327-a-041 figure 42. input offset voltage vs. input common-mode voltage, v s = +3 frequency (hz) cmrr (db) 1k 10k 100k 1m 10m 100m 0 20 40 60 80 100 120 03327-a-042 figure 43. cmrr vs. frequency frequency (hz) pssr (db) 100 1k 10k 100k 1m 10m 100m 1g ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?psrr +psrr 03327-a-043 figure 44. psrr vs. frequency
ad8027/ad8028 rev. b | page 14 of 24 frequency (hz) off isolation (db) 10k 100k 1m 10m 100m 1g ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 v in = 0.2v p-p g = +1 select = low 03327-a-044 figure 45. off isolation vs. frequency load resistance ( ? ) output saturation voltage (mv) 100 1000 10000 ?200 200 150 100 50 0 ?50 ?100 ?150 v s = +3v v s = +5v v s = 5v v oh ? v s+ v ol ? v s? load resistance tied to midsupply 03327-a-045 figure 46. output saturation voltage vs. output load frequency (hz) 1k 10k 100k 1m 10m 100m 1g 0.001 0.01 0.1 1 10 100 output impedance ( ? ) g = +2 g = +1 g = +5 03327-a-046 figure 47. output enabled impedance vs. frequency temperature (c) output saturation voltage (mv) ?40 ?25 ?10 5 20 35 50 65 80 110 95 125 25 30 35 40 45 v ol ? v s? v s = +5v r l = 1k ? tied to midsupply v s+ ? v oh 03327-a-047 figure 48. output saturation voltage vs. temperature i load (ma) open-loop gain (db) 0 102030405060 60 130 70 80 90 100 110 120 5v +5v +3v 03327-a-048 figure 49. open-loop gain vs. load current frequency (hz) output impedance ( ? ) 100k 1m 10m 100m 1g 10 100 1k 10k 100k 1m select = low 03327-a-049 figure 50. output disabledimpedance vs. frequency
ad8027/ad8028 rev. b | page 15 of 24 select voltage (v) select current ( a) 0 0.5 1.0 1.5 2.0 2.5 3.0 ?80 ?60 ?40 ?20 0 20 40 60 80 v s = +5v v s = +10v @ +25c +125c +25c ?40c 03327-a-050 figure 51. select pin current vs. select pin voltage and temperature time (ns) output voltage (v) 0 50 100 150 200 250 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 select pin (?2.0v to ?0.5v) output r l = 1k ? r l = 100 ? r l = 10k ? g = ?1 v s = 2.5v v in = ?1.0v 03327-a-051 figure 52. enable turn-on timing time ( s) output voltage (v) 0.512345678910 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 g = ?1 v s = 2.5v v in = ?1.0v select pin (?2.0v to ?0.5v) r l = 1k ? r l = 100 ? output r l = 10k ? 03327-a-052 figure 53. disable turn-off timing temperature (c) supply current (ma) ?40 ?25 ?10 5 20 35 50 65 80 110 95 125 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 v s = +3v v s = +5v v s = 5v 03327-a-053 figure 54. quiescent supply current vs. supply voltage and temperature
ad8027/ad8028 rev. b | page 16 of 24 theory of operation the ad8027/ad8028 is a rail-to-rail input and output amplifier designed in analog devices xfcb process. the xfcb process enables the ad8027/ad8028 to run on 2.7 v to 12 v supplies with 190 mhz of bandwidth and over 100 v/s of slew rate. the ad8027/ad8028 has 4.3 nv/ hz of wideband noise with 17 nv/ hz noise at 10 hz. this noise performance, with an offset and drift performance of less than 900 v maximum and 1.5 v/c typical, respectively, makes the ad8027/ad8028 ideal for high speed precision applications. additionally, the input stage operates 200 mv beyond the supply rails and shows no phase reversal. the amplifier features overvoltage protection on the input stage. once the inputs exceed the supply rails by 0.7 v, esd protection diodes will turn on, drawing excessive current through the differential input pins. a series input resis- tor should be included to limit the input current to less than 10 ma. input stage the rail-to-rail input performance is achieved by operating complementary input pairs. which pair is on is determined by the common-mode level of the differential input signal. look- ing at the schematic in figure 55, a tail current (i tail ) is gener- ated that sources the pnp differential input structure consisting of q1 and q2. a reference voltage is generated internally that is connected to the base of q5. this voltage is continually com- pared against the common-mode input voltage. when the common-mode level exceeds the internal reference voltage, q5 diverts the tail current (i tail ) from the pnp input pair to a cur- rent mirror that sources the npn input pair consisting of q3 and q4. the npn input pair can now operate 200 mv above the positive rail. both input pairs are protected from differential input signals above 1.4 v by four diodes across the input (see figure 55). in the event of differential input signals that exceed 1.4 v, the diodes will conduct and excessive current will flow through them. a series input resistor should be included to limit the input current to 10 ma. crossover selection a new feature available on the ad8027/ad8028, which is called crossover selection, allows the user to choose the crossover point between the pnp/npn differential pairs. although the crossover region is small, operating in this region should be avoided since it can introduce offset and distortion to the out- put signal. to help avoid operating in the crossover region, the ad8027/ad8028 allows the user to select from two preset crossover locations (i.e., voltage levels) using the select pin. looking at the schematic in figure 55, the crossover region is about 200 mv and is defined by the voltage level at the base of q5. internally, two separate voltage sources are created approxi- mately 1.2 v from either rail. one or the other is connected to q5 based on the voltage applied to the select pin. this allows for either dominant pnp pair operation, when the select pin is left open, or dominant npn pair operation, when the select pin is pulled high. this pin also provides the tradi- tional power-down function when it is pulled low. this allows the designer to achieve the best precision and ac performance for high-side and low-side signal applications. see figure 50 through figure 53 for select pin characteristics. vcc 1.2v + ? vee i tail 1.2v + ? logic v sel vp q5 q3 q1 q2 q4 vn voutp voutn i cmfb vcc vee i cmfb 03327-a-054 figure 55. simplified input stage
ad8027/ad8028 rev. b | page 17 of 24 in the event that the crossover region cannot be avoided, spe- cific attention has been given to the input stage to ensure con- stant transconductance and minimal offset in all regions of operation. the regions are: pnp input pair running, npn input pair running, and both running at the same time (in the 200 mv crossover region). maintaining constant transconduc- tance in all regions ensures the best wideband distortion per- formance when going between these regions. with this tech- nique, the ad8027/ad8028 can achieve greater than 80 db sfdr for a 2 v p-p, 1 mhz, g = +1 signal on 1.5 v supplies. another requirement in achieving this level of distortion is the offset of each pair must be laser trimmed to achieve greater than 80 db sfdr, even for low frequency signals. output stage the ad8027/ad8028 uses a common-emitter output structure to achieve rail-to-rail output capability. the output stage is designed to drive 50 ma of linear output current, 40 ma within 200 mv of the rail, and 2.5 ma within 35 mv of the rail. loading of the output stage, including any possible feedback network, will lower the open-loop gain of the amplifier. refer to figure 49 for the loading behavior. capacitive load can degrade the phase margin of the amplifier. the ad8027/ad8028 can drive up to 20 pf, g = +1 as seen in figure 10. a small (25 ? to 50 ?) series resistor (r snub ) should be included if the capacitive load is to exceed 20 pf for a ga in of 1. increasing the closed- loop gain will increase the amount of capacitive load that can be driven before a series resistor will need to be included. dc errors the ad8027/ad8028 uses two complementary input stages to achieve rail-to-rail input performance, as mentioned in the input stage section. to use the dc performance over the entire common-mode range, the input bias current and input offset voltage of each pair must be considered. referring to figure 56, the output offset voltage of each pair is calculated by ? ? ? ? ? ? ? ? + = g f g pnp os out pnp os r r r v v , , , , ? ? ? ? ? ? ? ? + = g f g npn os out npn os r r r v v , , , where the difference of the two will be the discontinuity experi- enced when going through the crossover region. the size of the discontinuity is defined as ( ) ? ? ? ? ? ? ? ? + ? = g f g npn os, pnp os, dis r r r v v v using the crossover select feature of the ad8027/ad8028 helps to avoid this region. in the event that the region cannot be avoided, the quantity ( v os, pnp C v os, npn ) is trimmed to minimize this effect. because the input pairs are complementary, the input bias current will reverse polarity when going through the cross over region shown in figure 37. the offset between pairs is described by () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? = ? f g f g s npn b, pnp b, npn os, pnp os, r r r r r i i v v i b, pnp is the input bias current of either input when the pnp input pair is active, and i b, npn is the input bias current or either input pair when the npn pair is active. if r s is sized so that when multiplied by the gain factor it equals r f , this effect will be eliminated. it is strongly recommended to balance the imped- ances in this manner when traveling through the crossover region to minimize the dc error and distortion. as an example, assuming the pnp input pair has an input bias current of 6 a and the npn input pair has an input bias current of C2 a, a 200 v shift in offset will occur when traveling through the crossover region with r f equal to 0 ? and r s equal to 25 ?. in addition to the input bias current shift between pairs, each input pair has an input bias current offset that will contribute to the total offset in the following manner f b g f g s b os r i r r r r i v ? + ? ? ? ? ? ? ? ? ? + = ? v out i b + r f r g i b ? v os r s +? +? v i + ? select ?v +v ? + ad8027/ ad8028 03327-a-055 figure 56. op amp dc error sources
ad8027/ad8028 rev. b | page 18 of 24 wideband operation voltage feedback amplifiers can use a wide range of resistor values to set their gain. proper design of the applications feed- back network requires consideration of the following issues: ? poles formed by the amplifiers input capacitances with the resistances seen at the amplifiers input terminals ? effects of mismatched source impedances ? resistor value impact on the applications voltage noise ? amplifier loading effects the ad8027/ad8028 has an input capacitance of 2 pf. this input capacitance will form a pole with the amplifiers feedback network, destabilizing the loop. for this reason, it is generally desirable to keep the source resistances below 500 ?, unless some capacitance is included in the feedback network. likewise, keeping the source resistances low will also take advantage of the ad8027/ad8028s low input referred voltage noise of 4.3 nv/ hz . with a wide bandwidth of over 190 mhz, the ad8027/ad8028 has numerous applications and configurations. the ad8027/ad8028 shown in figure 57 is configured as a nonin- verting amplifier. the inverting configuration is shown in figure 58 and an easy selection table of gain, resistor values, bandwidth, slew rate, and noise performance is presented in table 5. +v ?v c2 10 f c1 0.1 f c4 0.1 f c3 10 f v out r g r1 r f select v in r1 = r f ||r g ad8027/ ad8028 + ? 03327-a-056 figure 57. wideband noninverting gain configuration +v ?v c2 10 f c1 0.1 f c4 0.1 f c3 10 f r1 c5 v out r g r1 = r f ||r g r f v in select ad8027/ ad8028 + ? 03327-a-057 c f figure 58. wideband inverting gain configuration table 5. component values, bandwidth, and noise performance (v s = 2.5 v) noise gain (noninverting) r source (?) r f (?) r g (?) C3 db ss bw (mhz) output noise with resistors (nv/ hz ) 1 50 0 n/a 190 4.4 2 50 499 499 95 10 10 50 499 54.9 13 45
ad8027/ad8028 rev. b | page 19 of 24 circuit considerations balanced input impedances balanced input impedances can help improve distortion per- formance. when the amplifier transitions from pnp pair to npn pair operation, a change in both the magnitude and direc- tion of the input bias current will occur. when multiplied times imbalanced input impedances, a change in offset will result. the key to minimizing this distortion is to keep the input imped- ances balanced on both inputs. figure 59 shows the effect of the imbalance and degradation in distortion performance for a 50 ? source impedance, with and without a 50 ? balanced feed- back path. frequency (mhz) 0.1 1 10 20 distortion (db) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 g = +1 v out = 2v p-p r l = 1k ? v s = +3v r f = 24.9 ? r f = 49.9 ? r f = 0 ? 03327-a-058 figure 59. sfdr vs. frequency and various r f pcb layout as with all high speed op amps, achieving optimum perform- ance from the ad8027/ad8028 requires careful attention to pcb layout. particular care must be exercised to minimize lead lengths of the bypass capacitors. excess lead inductance can influence the frequency response and even cause high fre- quency oscillations. the use of a multilayer board, with an internal ground plane, will reduce ground noise and enable a tighter layout. to achieve the shortest possible lead length at the inverting input, the feedback resistor, r f , should be located beneath the board and span the distance from the output, pin 6, to the input, pin 2. the return node of the resistor r g should be situated as closely as possible to the return node of the negative supply bypass capacitor connected to pin 4. on multilayer boards, all layers underneath the op amp should be cleared of metal to avoid creating parasitic capacitive elements. this is especially true at the summing junction (i.e., the Cinput). extra capacitance at the summing junction can cause increased peaking in the frequency response and lower phase margin. grounding to minimize parasitic inductances and ground loops in high speed, densely populated boards, a ground plane layer is critical. understanding where the current flows in a circuit is critical in the implementation of high speed circuit design. the length of the current path is directly proportional to the magnitude of the parasitic inductances and thus the high frequency impedance of the path. fast current changes in an inductive ground return will create unwanted noise and ringing. the length of the high frequency bypass capacitor pads and traces is critical. a parasitic inductance in the bypass grounding will work against the low impedance created by the bypass capacitor. because load currents flow from supplies as well as ground, the load should be placed at the same physical location as the bypass capacitor ground. for large values of capacitors, which are intended to be effective at lower frequencies, the cur- rent return path length is less critical. power supply bypassing power supply pins are actually inputs and care must be taken to provide a clean, low noise dc voltage source to these inputs. the bypass capacitors have two functions: 1. provide a low impedance path for unwanted frequencies from the supply inputs to ground, thereby reducing the effect of noise on the supply lines. 2. provide sufficient localized charge storage, for fast switching conditions and minimizing the voltage drop at the supply pins and the output of the amplifier. this is usually accomplished with larger electrolytic capacitors. decoupling methods are designed to minimize the bypassing impedance at all frequencies. this can be accomplished with a combination of capacitors in parallel to ground. good quality ceramic chip capacitors should be used and always kept as close to the amplifier package as possible. a par- allel combination of a 0.01 f ceramic and a 10 f electrolytic covers a wide range of rejection for unwanted noise. the 10 f capacitor is less critical for high frequency bypassing, and in most cases, one per supply line is sufficient.
ad8027/ad8028 rev. b | page 20 of 24 applications using the ad8027/ad8028 select pin the ad8027/ad8028 features a unique select pin with two functions. the first is a power-down function that places the ad8027/ad8028 into low power consumption mode. in the power-down mode, the amplifier draws 450 a (typ) of supply current. the second function, as mentioned in the theory of operation section, shifts the crossover point (where the npn/pnp input differential pairs transition from one to the other) closer to either the positive supply rail or the negative supply rail. this selectable crossover point allows the user to minimize distortion based on the input signal and environment. the default state is 1.2 v from the positive power supply, with the select pin left floating or in tri-state. table 6 shows the required voltages and modes of the select pin. table 6. select pin mode control select pin voltage (v) mode v s = 5 v v s = +5 v v s = +3 v disable C5 to C4.2 0 to 0.8 0 to 0.8 crossover referenced C1.2 v to positive supply C4.2 to C3.3 0.8 to 1.7 0.8 to 1.7 crossover referenced +1.2 v to negative supply C3.3 to +5 1.7 to 5.0 1.7 to 3.0 when the input stage transitions from one input differential pair to the other, there is virtually no noticeable change in the output waveform. the disable time of the ad8027/ad8028 amplifier is load dependent. typical data is presented in table 7. see figure 52 and figure 53 for the actual switching measurements. table 7. disable switching speeds supply voltages (r l = 1 k?) 5 v +5 v +3 v t on 45 ns 50 ns 50 ns t off 980 ns 1100 ns 1150 ns driving a 16-bit adc with the adjustable crossover distortion selection point and low noise, the ad8028 is an ideal amplifier for driving or buffering input signals into high resolution adcs, such as the ad7677, a 16-bit, 1 lsb inl, 1 msps differential adc. figure 60 shows the typical schematic for driving the adc. the ad8028 driving the ad7677 offers performance close to non-rail-to- rail amplifiers and avoids the n eed for an additional supply, other than the single 5 v supply already used by the adc. in this application, the select pins are biased to avoid the crossover region of the ad8028 for low distortion operation. +5v +5v + ? ad8028 analog input + input range (0.15v to 2.65v) select (open) select (open) + ? analog input ? ad7677 +5v 16 bits 15 ? 15 ? 2.7nf 4mhz lpf 4mhz lpf 2.7nf 0.1 f 0.1 f ad8028 03327-a-059 figure 60. unity gain differential drive as seen in figure 61, the ad8028 and ad7677 combination offers excellent integral nonlinearity (inl). summary test data for the schematic shown in figure 60 is presented in table 8. table 8. adc driver performance, f c = 100 khz, v out = 4.7 v p-p parameter measurement second harmonic distortion C105db third harmonic distortion C102db thd C102 db sfdr 105 dbc code 0 16384 32768 49152 65536 ?1.0 ?0.5 0 0.5 1.0 inl (lsb) 03327-a-060 figure 61. integral nonlinearity
ad8027/ad8028 rev. b | page 21 of 24 band-pass filter in communication systems, active filters are used extensively in signal processing. the ad8027/ad8028 is an excellent choice for active filter applications. in realizing this filter, it is impor- tant that the amplifier has a large signal bandwidth of at least 10 the center frequency, f o . otherwise, a phase shift can occur in the amplifier, causing instability and oscillations. in the schematic shown in figure 62, the ad8027/ad8028 is configured as a 1 mhz band-pass filter. the target specifications are f o = 1 mhz and a C3 db pass band of 500 khz. start the design by selecting the following: f o , q , c1 , and r4. then using the equations shown below, calculate the remaining variables. the test data shown in figure 63 indicates that this design yielded a filter response with a center frequency f o = 1 mhz and a bandwidth of 450 khz. (mhz) (mhz) band pass f q o = k = 2 f o c1 c2 = 0.5 c1 r1 = 2/ k , r2 = 2/(3 k ), r3 = 4/ k h = 1/3(6.5 C 1/ q ) r5 = r4 /( h C 1) +5 ?5 c3 0.1 f c4 0.1 f r4 523 ? r5 523 ? c2 500pf c1 1000pf r3 634 ? v out r1 316 ? r2 105 ? v in select ad8027/ ad8028 + ? 03327-a-061 figure 62. band-pass filter schematic 0.1 ch1 s21 log 5db/ref 6.342db 1:6.3348db 1.00 000mhz 1 frequency ? mhz 10 1 03327-a-062 figure 63. band-pass filter response design tools and technical support analog devices is committed to simplifying the design process by providing technical support and online design tools. we offer technical support via free evaluation boards, sample ics, inter- active evaluation tools, data sheets, spice models, application notes, phone and email support, all of which are available at www. analog.com .
ad8027/ad8028 rev. b | page 22 of 24 outline dimensions 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarit y 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in desig n compliant to jedec standards ms-012aa figure 64. 8-lead standard small outline package, narrow body [soic] (r-8) dimensions shown in millimeters and (inches) 13 4 5 2 6 2.90 bsc pin 1 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.22 0.08 0.60 0.45 0.30 10 4 0 0.50 0.30 0 .15 max 1.30 1.15 0.90 seating plane 1.45 max compliant to jedec standards mo-178ab figure 65. 6-lead plastic surface-mount package [sot-23] (rt-6) dimensions shown in millimeters 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 coplanarity 0.10 compliant to jedec standards mo - 187ba figure 66. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters
ad8027/ad8028 rev. b | page 23 of 24 esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide model minimum ordering quantity temperature rang e package description package outline branding ad8027ar 1 C40c to +125c 8-lead soic r-8 ad8027ar-reel 2,500 C40c to +125c 8-lead soic r-8 ad8027ar-reel7 1,000 C40c to +125c 8-lead soic r-8 ad8027art-r2 250 C40c to +125c 6-lead sot-23 rt-6 h4b ad8027art-reel 10,000 C40c to +125c 6-lead sot-23 rt-6 h4b ad8027art-reel7 3,000 C40c to +125c 6-lead sot-23 rt-6 h4b ad8028ar 1 C40c to +125c 8-lead soic r-8 ad8028ar-reel 2,500 C40c to +125c 8-lead soic r-8 ad8028ar-reel7 1,000 C40c to +125c 8-lead soic r-8 ad8028arm 1 C40c to +125c 10-lead msop rm-10 h5b AD8028ARM-REEL 3,000 C40c to +125c 10-lead msop rm-10 h5b AD8028ARM-REEL7 1,000 C40c to +125c 10-lead msop rm-10 h5b
ad8027/ad8028 rev. b | page 24 of 24 notes ? 2003 analog devices, inc. all rights reserved. trademarks and regis- tered trademarks are the property of their respective owners. c03327C0C10/03(b)

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